CXMT's 50% Bigger DRAM: 5 Numbers, One Verdict

Introduction

One memory die now holds fifty percent more data than the one before it. That is a big jump for a chip that was already packed tight. Five numbers explain how it was done. A sixth number, which was not published, decides how much it matters. We will grade all six.

You're watching Wafer Report. How chips are made, and what's new. By the end, you will know how to grade any DRAM process step on density, patterning and yield.

Context

The announcement is simple. CXMT has started mass production of its fifth-generation DRAM process, which it calls G5. The first products are twenty-four gigabit LPDDR5X chips, made for mobile devices. Twenty-four gigabits is three gigabytes on a single die. The previous comparable parts held sixteen gigabits.

Many headlines call G5 a twelve nanometre process. That is a simplification. The real figure is eleven point nine five nanometres, and it measures one specific dimension, called the active-area half-pitch. It is not a node name in the way logic chips use the term. So we will not compare names. We will compare measurements.

To grade a DRAM step, we ask three questions. Bit density: how many bits fit on one die? Patterning cost: how hard is it, and how many steps does it take, to print the shapes? Yield risk: how many finished dies will actually work? Every number in this video answers one of these. Keep them in mind.

How it works

First, a picture of a DRAM cell. One transistor and one capacitor. The capacitor holds a tiny electric charge. Charge present means one. Charge absent means zero. A single die holds billions of these cells, arranged in a grid. Shrink the grid, and the same die can hold more bits. That is the whole game.

Number one. Eleven point nine five nanometres. This is the active-area half-pitch. The active area is the silicon where the transistors are formed. Pitch is the distance from one active strip to the next repeat. Half-pitch is half of that distance. Here, the full pitch is twenty-three point nine nanometres. This answers our first question, bit density. A smaller pitch means more cells in the same space.

How do you print lines this close together? One exposure cannot easily do it. CXMT uses quadruple patterning. The idea is to split one hard pattern into four easier ones, built up through repeated deposition and etch steps. The final pitch is a quarter of what one exposure prints. CXMT says it also used digital simulation to develop the process. Each added step costs time, and adds a chance for error. This answers question two, patterning cost.

Number two. Six thousand seven hundred sixty-two nanometres. CXMT says its DRAM-optimized high-K metal gate process reduced the height of the core cell array to this figure. Here is a comparison from our own arithmetic. Divide six thousand seven hundred sixty-two by twenty-three point nine. The answer is about two hundred eighty-three. The array height equals roughly two hundred eighty-three pitch lengths. All else equal, a smaller array leaves more die area for cells.

Number three. Forty-five to one. This is the aspect ratio of the storage capacitor. As cells shrink, the capacitor cannot stay wide. So it grows deep. Picture a drinking straw standing on its end. Forty-five to one means the depth is forty-five times the width. CXMT says a modified process flow and new materials, which it did not name, made this possible.

SK hynix says capacitor aspect ratios will need to exceed one hundred to one once critical dimensions fall below ten nanometres. So forty-five to one is under half of that projection. This is not a flaw. It is a marker on the road, and it shows how much room is left before the next hard wall.

Why is deep so hard? First, etching. The hole must stay straight from top to bottom. Second, deposition. Thin layers must coat the bottom as evenly as the top. Third, stability. A tall, thin structure can lean. Analysts note that high aspect ratios make etching, deposition, mechanical stability and high-yield manufacturing considerably more challenging. This is where yield risk lives.

Number four. Fifty percent. That is the capacity gain per die. Twenty-four gigabits, against sixteen gigabits for existing products. It is the first of two fifty percents in this story. It answers question one at the product level. The chips come in two package formats, made for different mobile device designs.

Number five is also fifty percent. But it is a different fifty percent. CXMT says G5 yields at least fifty percent more gross dies per wafer than the previous generation. Look at the baseline. It is an eight gigabit chip, not the twenty-four gigabit part. So one number counts bits per die. The other counts dies per wafer.

Now notice the word gross. Gross dies are counted before defects are screened out. Yield is the share that actually works. CXMT has not disclosed yield. So nobody outside can compute good dies per wafer, or the cost per bit. It is like counting every loaf that enters the oven, without counting the ones that burn.

What it means

So what changes for you? You can now read a memory announcement with three questions, instead of one headline. And you can check each number for its unit, its baseline, and what it counts. Let us apply that to G5.

First check: is this number about a die, or about a wafer? Twenty-four gigabits is a die number. Fifty percent more gross dies is a wafer number. Second check: what is the baseline? Sixteen gigabits, or eight gigabits? Third check: was it measured before or after defect screening? These three checks catch most confusing memory headlines.

Now the verdict, one line for each question. Bit density: strong. Twenty-four gigabits per die and an eleven point nine five nanometre half-pitch are both reported. Patterning cost: real progress, with the cost unknown. Quadruple patterning works, and it adds steps. Yield risk: open. The one number that would settle it is missing. This is our opinion, based on the published figures.

What might this mean in practice? One die of three gigabytes is a larger building block. Sixteen gigabits gave two gigabytes. A device designer can reach a given memory size with fewer dies, if the parts perform as claimed. Power and speed figures have not been published, so we cannot yet say how they compare.

The other side

Here is the honest limit. Without yield and cost per bit, productivity cannot be verified. And eleven point nine five is one dimension. It does not let us assume equal speed, power or density with any other maker's parts. Also, forty-five to one sits well below the projected need for sub-ten-nanometre DRAM. The progress is real. The road ahead is still long.

Takeaway

The takeaway: G5 is real progress on density and patterning, and the missing number is yield. Read every memory headline by its unit, its baseline, and what it counts. Next, we look at how memory dies are stacked to make high-bandwidth memory.